One of the exciting new features of the Series 5000 chips and NodeBuilder® FX Development Tool is interrupt support. Interrupt support has been a frequent request from device manufacturers since it provides a reliable method to provide timely and deterministic response to a hardware event. The Series 5000 chips provide a unique architecture for supporting interrupts. The original Series 3000 Neuron core has three processors on one chip—one for the application, one for layers 3 to 6 of the ISO/IEC 14908-1 Control Network Protocol (CNP), and one for layer 2 of CNP. The Series 5000 chips add a fourth processor for interrupt use when the system clock is 20 MHz or higher. This provides fast context switching for interrupt handling without impacting the application or CNP stack.
This article describes and compares two example hardware and software designs of an application for the FT 5000 Smart Transceiver for a problem that is best solved with interrupt support. The requirement for this example is to periodically read data from a 12-bit A/D converter with a sample rate of at least 10 kHz, with minimal jitter, and no lost data points with continuous sampling, while also supporting batch data transfer to multiple devices and applications over the LonWorks® network. The main application may also calculate statistics about the sampled data including a moving average value, standard deviation, minimum value, maximum value, and time since last change.
Hardware
Two hardware designs were evaluated, one with an ADC with a parallel interface and one with an ADC with a serial interface. Design considerations for one of each type of ADC are described in the following sections.
ADC
For the parallel ADC design, the requirements for the ADC for this example are a device with an 8-bit parallel I/O bus requiring no more than 12 I/O lines and a fast conversion time of no more than 100 µs for up to a 10 kHz sample rate. An example part is a Maxim MX574A 12-Bit A/D Converter. It supports up to a 40 kHz sample rate with a 25 µs maximum conversion time, has an 8-bit parallel I/O bus, and requires 4 handshake/control lines for a total of 12 I/O lines. The FT 5000 Smart Transceiver can support this interface, but would have no available I/O for other uses.
For the serial ADC design, the requirements for the ADC for this example are a device with an SCI, SPI, or I2C interface, also supporting a fast conversion time of no more than 100 µs for up to a 10 kHz sample rate. An example part is a Microchip MCP3202 Dual Channel 12-Bit A/D Converter with SPI Serial Interface. The SPI interface requires only 4 I/O lines, leaving 8 open I/O lines on the FT 5000 chip while supporting two analog inputs instead of the one analog input supported by the MX574A. The MCP3202 supports up to a 100 kHz sample rate depending on the supply voltage, which can be 2.7 to 5 VDC.
Sample-and-Hold
For the parallel ADC design, according to the MX574A data sheet the analog input to the MX574A ADC must be stable to within ½ LSB during the entire conversion for 12-bit accuracy. This limits the input signal bandwidth to a couple of hertz for sinusoidal inputs. To support monitoring an input that changes at a rate greater than a couple hertz, the data sheet recommends an Analog Devices AD585 Sample-and-Hold Interface to keep the analog input stable during each measurement period.
For the serial ADC design, the MCP3202 ADC includes an integrated sample-and-hold circuit, eliminating the need for an external sample-and-hold chip. The sample-and-hold circuit works best with a very low impedance input. The MCP3202 data sheet recommends an operational amp on the input such as the Microchip MCP601 which has an output impedance of tens of ohms. This is a much lower cost part than the AD585 Sample-and-Hold Interface. The Microchip MCP602 is a dual-channel version of the MCP601, which makes it a good match for the MCP3202.
Processor
The host for this application will be an Echelon FT 5000 EVB. This board is a complete Series 5000 LonWorks device that is useful for prototyping and testing new LonWorks devices. The board includes an FT 5000 Smart Transceiver supporting up to an 80 MHz system clock, 64 KB serial EEPROM, 64 KB flash memory, 4 x 20 character LCD, 4-way joystick with center push button, 2 push-button inputs, 2 LED outputs, a light-level sensor, and temperature sensor. Since all the I/O pins of the FT 5000 Smart Transceiver would be required for the parallel ADC, the on-board I/O included on the FT 5000 EVB would have to be disconnected from the Smart Transceiver for the parallel design. Some of the on-board I/O can be used for the serial design.
Power Supply
For the parallel ADC design, the MX574A ADC requires a ±15 VDC power supply. The FT 5000 EVB is powered by a 9VDC power supply and has 3.3V and 5V outputs to any attached I/O board. A TDK-Lambda CC-E Series 5V to ±15 VDC dual output DC-DC converter can be used to generate the 15V outputs.
For the serial ADC design, the MCP602 has the same single supply voltage requirements as the MCP3202 ADC, which is compatible with both the 3.3V and 5V outputs of the FT 5000 EVB, so no additional power supply is required for the serial ADC other than what is supplied by the FT 5000 EVB.
Software
System Timer
The new Series 5000 system timer will be used to generate a jitter-free periodic interrupt. The system timer can be configured to generate periodic interrupts at a 2.4 kHz to 625 kHz range. An empty interrupt task and application on a Series 5000 chip is limited to about a 70 kHz interrupt rate. This application will be doing some processing in the interrupt tasks, so the actual limit is more likely to be around 10 kHz. This application will be a good opportunity to test that limit. The code to use the system timer for period interrupts is very simple. The following code creates an interrupt task that executes at a 10 kHz rate:
interrupt (repeating, "10kHz") {
}
The code within this interrupt task will start an ADC conversion for both the parallel and serial ADCs, and will also read the ADC data for the serial ADC as described in the next section.
ADC Interrupt Task
For the parallel ADC, a second interrupt task will be created to respond to the end-of-conversion (EOC) input from the ADC. For the example, the EOC input will be received on IO11. The following code creates an interrupt task that executes when the EOC input changes from low to high:
interrupt (IO_11, clockedge(+)) {
}
The code within this interrupt task will read the new value from the ADC and write it to a queue.
For the serial ADC, the built-in SPI interrupt service task will be used to receive the SPI data, taking the place of the parallel ADC interrupt task. The built-in SPI task will transfer the 2 bytes of data from the 16-byte hardware FIFO to an input buffer. This data will be read in the system timer interrupt task prior to starting the next conversion. That is, during system clock interrupt task n, a conversion will be started and an I/O read from the ADC will also be started. Between system clock interrupt task n and interrupt task n + 1, the SPI interrupt task will receive the new value and buffer it. The buffered value will be read in interrupt task n + 1.
Interrupt Enable
The Neuron C application can control when interrupts are enabled and disabled. They should only be enabled when the application is configured and online. Following is the required code to get the application state and conditionally enable interrupts on reset, and to enable and disable interrupts when the application state is changed to online and offline.
#include "status.h"
when (reset) {
// Query device status
status_struct status;
retrieve_status(&status);
// Initialize device
// ...
// Enable interrupt system if configured and online
if (status.status_node_state == 0x04) {
interrupt_control(INTERRUPT_IO | INTERRUPT_REPEATING);
}
}
when (offline) {
interrupt_control(0);
}
when(online) {
interrupt_control(INTERRUPT_IO | INTERRUPT_REPEATING);
}
Internal Data Transfer
The processing in the interrupt task must be kept to a minimum for rapidly repeating interrupts such as the ADC interrupt. The system timer interrupt task only has to start an ADC conversion, so will be quite short. The system timer (for the serial ADC) or ADC interrupt (for the parallel ADC) task should only read the new value from the ADC, and then queue the value for further processing by one of the application when tasks. Application when tasks can store the data to a data log, calculate statistics, and manage the data transfer to other devices and applications.
Both the application when tasks and the system or ADC interrupt task will require access to the queue with ADC data values. The interrupt task will be adding them to the queue and the application when tasks will be reading and clearing them from the queue. A semaphore is required to ensure coordinated access to the shared data. The new Neuron C __lock statement will be used to ensure reliable access to the ADC data by the interrupt and when tasks. Following is example code from the parallel ADC implementation for using the __lock statement.
interrupt(IO_11, clockedge(+)) {
unsigned newData;
newData = ...
...
__lock {
Enqueue(newData);
}
}
boolean DataAvailable(void) {
boolean result;
__lock {
result = !QueueIsEmpty();
}
return result;
}
when (DataAvailable()) {
__lock {
unsigned data;
while(Dequeue(&data)) {
...
}
}
}
External Data Transfer
The when (DataAvailable()) task described in the previous section will dequeue data values received from the ADC, calculate statistics on the data, store the data in a circular data log, and make the data log and statistics available to other devices and applications. The new standard Data Logger profile will be used to make the data log available to multiple hosts. This profile introduces a new data log transfer protocol that provides a lightweight and stateless method to transfer data log contents to other devices and applications. Using a stateless protocol has the benefit of supporting data log access by multiple hosts simultaneously. The new Data Logger profile is available in the draft 13.02 standard resource file set.
Next Steps
The serial design is lower cost and requires fewer pins and a simpler power supply than the parallel design, while providing comparable performance. If there is sufficient interest, I will start developing the serial version of the application outlined in this paper on an FT 5000 EVB using a second FT 5000 EVB to simulate the ADC interface. This will give me a chance to debug the application before the hardware is ready. If you have any suggestions for applications or hardware changes, please let me know. You can leave a comment or suggestion.
